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Microchip Technology /ATSAME70J20 /PMC /PCR

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Interpret as PCR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0PID0 (SLOW_CLK)GCLKCSS 0 (CMD)CMD 0GCLKDIV0 (EN)EN 0 (GCLKEN)GCLKEN

GCLKCSS=SLOW_CLK

Description

Peripheral Control Register

Fields

PID

Peripheral ID
GCLKCSS

Generic Clock Source Selection

0 (SLOW_CLK): Slow clock is selected

1 (MAIN_CLK): Main clock is selected

2 (PLLA_CLK): PLLACK is selected

3 (UPLL_CLK): UPLL Clock is selected

4 (MCK_CLK): Master Clock is selected
CMD

Command
GCLKDIV

Generic Clock Division Ratio
EN

Enable
GCLKEN

Generic Clock Enable

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data